Currently, however, it is becoming one of the most critical. In the past, simulation was not an important stage in the FPGA design flow.
#Fpga simulation tools verification
FPGA designs are growing in complexity and the traditional verification methodologies are no longer sufficient. Today’s FPGAs need both functional and timing simulation in order to ensure that designs work and continue to work. Furthermore there is an escalating challenge for the design and verification engineer (which many times can be the same person) to get proper testing of today’s FPGA designs in shorter timeframes with an increased confidence of first-pass success.
#Fpga simulation tools full
With FPGAs growing in speed, density and complexity, there is a lot of taxation not only on manpower but also on computer processors and available memory to complete a full timing verification. One of the biggest challenges that FPGA design and verification engineers face today is time and resource constraints. This cuts into the time-to-market and cost-of-implementation advantages of using FPGAs in the first place. Timing simulations that traditionally were measured in the hours, sometimes minutes, using standard desktop computers can now for some projects be measured in multiple days or weeks requiring high-powered 64-bit servers. Timing simulation can be the most revealing verification method however, it is often one of the most difficult and time consuming for many designs. By Premduth Vidyanandan, Xilinx Inc., Longmont, CO, the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods.
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